The present invention relates to a semiconductor memory, for example, a semiconductor memory to synchronize input of a command and write or read of data with an external clock, such as a synchronous DRAM.
In the case of semiconductor memory which synchronizes input of a command and write or read of data with an external clock, the operation of circuits in a chip is synchronized with some basic pulses, which are generated within the chip by using the external clock as a trigger. In such a semiconductor memory, an access time from input of read command to data output is determined by the number of pulses in the external synchronous clock. For example, in a synchronous DRAM, the number of the pulses in the external synchronous clock is called as CAS latency (CL) and it is important value for a specification. A column operation synchronous pulse, which is synchronized with the operation of the column system circuit within a chip, is generated at a timing to fill this value. Further, the timing of this column operation synchronous pulse is usually determined uniquely by the above CL. The same pulse can be used even if a column command represents xe2x80x9creadxe2x80x9d or xe2x80x9cwritexe2x80x9d, since the pulse control is advantageously simplified when the column operation synchronous pulses of read and write are identical.
FIGS. 1 to 3 illustrate the above described conventional semiconductor memory, respectively. FIG. 1 is a block diagram showing extractively a circuit in reference to the control of a column system basic pulse in the synchronous DRAM. FIG. 2 is a circuit diagram showing a constitutional example of an input column address latch controller in the circuit shown in FIG. 1. FIG. 3 is a circuit diagram showing a column pulse transfer controller in the circuit shown in FIG. 1.
As shown in FIG. 1, a circuit in reference to the control of the column system basic pulse in the synchronous DRAM comprises an external clock input buffer 11, pulse generators 12-1, 12-2, 13-1, 13-2, delay circuits 14-1, 14-2, a CAS input buffer 15, a RAS input buffer 16, a CS input buffer 17, a decoder 18, a decoder and latch circuit 19, a WE input buffer 20, an input column address latch controller 21, address input buffers 22-1, 22-2 (ADD1, ADD2), address latches 23-1, 23-2, core buses 24-1, 24-2 (addresses K1, K2), a burst length counter 25, a column pulse transfer controller 26, a column bank controller 27, a DQ buffer 28, a data line 29, an off chip driver 30, an output pulse generator 31, transfer gates 32-1 to 32-7, 32-9 to 32-12, a column address decoder 33, a memory cell allay 34 and an inverter 35 or the like.
As shown in FIG. 2, the above column address latch controller 21 is composed of a NAND gate 41, a transfer gate 42 and inverters 43, 44, 45.
Further, as shown in FIG. 3, the above column pulse transfer controller 26 is composed of a NOR gate 51, transfer gates 52 to 54 and inverters 55 to 60. A signal CL2OPN controls the transfer gate 52 to open the transfer gate 52 when the CAS latency is 2. A signal CL3OPN controls the transfer gate 53 to open the transfer gate 52 when the CAS latency is 3.
In FIGS. 1 to 3, in order to simplify the illustrations, it is shown that only one-sided MOS transistor gates of transfer gates 32-1 to 32-7, 32-9 to 32-12, 42, 52 to 54 are provided with signals. However, other sided MOS transistor gates are provided with inverted ones of the above signals. Here, the transfer gates 32-1 to 32-7, 32-9 to 32-12, 42, 52 to 54 are formed by connecting a current path of a P channel type MOS transistor and a current path of an N channel type MOS transistor in parallel.
In this example, two kinds of column system basic pulses are used for a column operation synchronization and a column address latch. These two kinds of column system basic pulses are activated at the same timing.
FIGS. 4 and 5 are timing charts for showing signal waveforms of the CL2 and the CL3 schematically. FIG. 4 shows a signal waveform in the case that the CL2, i.e., the CAS latency is 2 and FIG. 5 shows a signal waveform in the case that the CL3, i.e., the CAS latency is 3, respectively.
As shown in FIG. 1, the external clock input buffer 11 is connected to two pulse generators 12-1 and 13-1. As shown in the timing chart of FIG. 4, respective pulse generators 12-1 and 13-1 generate pulse signals Pa and Pb, which have different pulse widths each other, from leading edges of an external clock VCLK. These respective pulse generators 12-1 and 13-1 are connected to pulse generators 12-2 and 13-2 via delay circuits 14-1 and 14-2, which are composed identically, respectively. These pulse generators 12-2 and 13-2 generate pulse signals Paxe2x80x2 and Pbxe2x80x2 from edges of the above pulse signals Pa and Pb, respectively. The pulse generators 12-1, 13-1 and 12-2, 13-2 are identically composed. The pulse signals Paxe2x80x2, Pbxe2x80x2 are obtained by shifting the pulse signals Pa, Pb for a certain period of time, respectively. In the present example, as described later, it is assumed that the pulse signals Pb, Pbxe2x80x2 are used for the column operation synchronous pules and the pulse signals Pa, Paxe2x80x2 are mainly used for the column address latch pulse.
If the column access information is inputted from a command pin, a decoder 18 is connected to the CAS input buffer 15, the RAS input buffer 16 and the CS input buffer 17, respectively, to decode these signals and generate a column system activated signal Pc. Further, the decoder and the latch circuit 19 is connected to the WE input buffer 20 in addition to the CAS input buffer 15, the RAS input buffer 16 and the CS input buffer 17. If the inputted command is write, the decoder and the latch circuit 19 activates a write enable signal Pe. If the inputted command is read, it activates a read enable signal Pf, respectively.
When the column system activated signal Pc is activated, the input column address latch controller 21 outputs a column address entry pulse Pd. This pulse Pd opens the transfer gates 32-6 and 32-7. Therefore, the address information of the address input buffers 22-1 and 22-2 are transferred to the address latches 23-1 and 23-2 in a column address counter 39, so that addresses K1 and K2 of the core buses 24-1 and 24-2 are decided.
On the other hand, activation of the column system activated signal Pc allows the burst length counter 25 to be activated. The pulse signal Pb counts up the activated burst length counter 25 by number of times corresponding to the burst length. During this time, the activated burst length counter 25 is activating a burst operation activated signal Pg.
As understood from the circuit construction shown in FIG. 3, in the case that the CAS latency is 2(CL2), the column pulse transfer controller 26 activates a column pulse transfer signal Pj soon after the burst operation activated signal Pg is activated. This column pulse transfer signal Pj opens the transfer gates 32-3 and 32-4 to transfer the pulse signal Paxe2x80x2 to the column bank controller 27 as a column operation synchronous pulse Pp and transfer the pulse signal Pbxe2x80x2 to the address latches 23-1 and 23-2 in a column address counter 39 as a column address latch pulse Pq. At this time, by the inverter 35, a inverted signal of the above column address latch pulse Pq is also transferred to the address latches 23-1 and 23-2.
In the present example, there is a margin in the activating timing of the column pulse transfer signal Pj with respect to the timing for activating these pulse signals Paxe2x80x2 and Pbxe2x80x2. Therefore, finding a logical OR of the column system activated signal Pc and the burst operation activated signal Pg, the column pulse transfer signal Pj is generated.
Using the column operation synchronous pulse Pp as a trigger, the column bank controller 27 generates a write pulse Pl when the write enable signal Pe is active and generates a read pulse Pm when the read enable signal Pf is active. The write pulse Pl opens a write gate of the DQ buffer 28 in a memory cell portion MCA. As a result, it becomes possible to write into the memory cell allay 34. Further, the read pulse Pm opens a read gate of the above DQ buffer 28 to output a cell data Pn to the data line 29. The cell data Pn of the above data line 29 is transferred to the off chip driver 30. After inputting a command, if the external clock VCLK at second cycles becomes active, the output pulse generator 31 outputs an output pulse Po by using the activated external clock VCLK as a trigger. This output pulse Po opens the transfer gate 32-5, which is arranged on the output terminal of the off chip driver 30. Then, an output data Dout is outputted to catch up with the external clock VCLK at third cycles.
On the other hand, while the column address latch pulse Pq, which is activated at the same time as the column operation synchronous pulse Pp, has been generated, the transfer gates 32-10 and 32-12 as backward registers are closed. The transfer gates 32-10 and 32-12 are located within the address latches 23-1 and 23-2 in the column address counter 39. During read and write operation to the memory cell portion MCA as the column operation synchronous pulse Pp as a trigger, the core bus addresses K1 and K2 are latched. The column operation synchronous pulse Pp is generated at the same time as the column address latch pulse Pq. Further, at the same time, the transfer gates 32-9 and 32-11 as forward registers are opened and the address information at a single digit before is recorded in this register. Hereby, the information of the address latch 23-1 is transferred to the address latch 23-2. If the pulse Pq is deactivated, the transfer gates 32-10 and 32-12 as the backward registers are opened to output the recorded address information at a single digit before to the core buses 24-1 and 24-2.
In the case of CL3, as understandably from the timing chart in FIG. 5, the burst operation activated signal Pg turns to a column pulse transfer signal Ph with being delayed by one cycle by the pulse signal Pb at the register within the column pulse transfer controller 26. In other words, the pulse signals Pa and Pb are transferred as the column operation synchronous pulse Pp and the column address latch pulse Pq with being delayed from the command input by one cycle, so that the access to the memory cell portion MCA is also delayed from the command input by one cycle and the date is outputted to catch up with the external clock VCLK at fourth cycle.
Next, the case that the write command is interrupted during the read operation of the CL2 and the CL3 is considered. As shown in FIG. 4, in the case of the CL2, upon inputting the write command, latches of the core bus addresses K1 and K2 due to the column address latch pulse Pq are released. Accordingly, the latching of the address is the same as that upon normal input of commands. On the contrary, in the case of the CL3, as shown in FIG. 5, when the write command is inputted, the core bus addresses K1 and K2 are latched in response to the column address latch pulse Pq. Therefore, the addresses ADD1 and ADD2 are latched from the address input buffers 22-1 and 22-1 to be held in the address latches 23-1 and 23-3 within the counter at once. Then, after the column address latch pulse Pq is inactive, the addresses ADD1 and ADD2 are outputted to the core buses 24-1 and 24-2.
As described above, using the same column operation synchronous pulse in read and write, there is a merit such that a system for latching the address when the column command interrupts during the column burst operation.
In the mean time, in the above described conventional synchronous DRAM, as shown in FIGS. 6 and 7, after the completion of the write burst, the case that a precharge command is inputted at the next cycle. FIG. 6 is a timing chart illustrating the operation in the case that the CAS latency is 2(CL2) and FIG. 7 is a timing chart illustrating the operation in the case that the CAS latency is 3(CL3). Here, a time from writing by the write pulse Pm to resetting of the word line WL is determined as tWR. The time from input of the precharge command to the word line reset is not changed in the CL2 and the CL3. On the other hand, the timing of the column operation synchronous pulse is uniquely determined by the CAS latency, which is important for determining a timing of the read operation. In other words, even when the column command is read or write, in the column operation synchronous pulse, the CL3 is delayed than the CL2. Therefore, if the CAS latency is 3 (CL3), tWR is smaller than in the case where the CAS latency is 2 (CL2). Consequently, a word line WL is reset before the data is completely written into a memory cell immediately before precharging.
An object of the present invention is to provide a semiconductor memory, which is capable of sufficiently securing an operational margin of a column system circuit.
The object of the present invention is attained by a semiconductor memory for synchronizing at least a part of input of a command and write or read of data with an external clock and generating a column operation synchronous pulse having the same number as that of a burst length within the semiconductor memory by using an internal operation synchronous pulse having the external clock as a trigger and after inputting a column system command, using the internal operation synchronous pulse as a trigger comprising a first path to which a first column operation synchronous pulse is transferred during read; a second path to which a second column operation synchronous pulse, which is different from the first column operation synchronous pulse, is transferred during write; and a switching circuit for selectively switching the first path and the second path.
Further, the object of the present invention is attained by a semiconductor memory for synchronizing input of a command and write or read of data with an external clock and generating a column operation synchronous pulse having the same number as that of a burst length within the semiconductor memory by using an internal operation synchronous pulse having the external clock as a trigger and after inputting a column system command, using the internal operation synchronous pulse as a trigger comprising a first pulse generator for generating a first column operation synchronous pulse for read within a chip with an external clock as a trigger; a second pulse generator for generating a second column operation synchronous pulse for read within a chip with the external clock as a trigger; a first signal line provided with a first column operation synchronous pulse for read to be outputted from the first pulse generator during read; a second signal line provided with a second column operation synchronous pulse for write to be outputted from the second pulse generator during read; and a column pulse transfer controller for controlling transfer of a first column operation synchronous pulse from the first pulse generator to the first signal line and transfer of a second column operation synchronous pulse from the second pulse generator to the second signal line, respectively.
Still further, the object of the present invention is attained by a synchronous DRAM comprising a first pulse generator for generating a first column operation synchronous pulse for read within a chip with an external clock as a trigger; a second pulse generator for generating a second column operation synchronous pulse for read within a chip with the external clock as a trigger; a first signal line provided with a first column operation synchronous pulse for read to be outputted from the first pulse generator during read; a second signal line provided with a second column operation synchronous pulse for write to be outputted from the second pulse generator during read; a first transfer gate to be arranged between the first pulse generator and the first signal line; a second transfer gate to be arranged between the second pulse generator and the second signal line; and a column pulse transfer controller for controlling the first and second transfer gate and controlling transfer of a first column operation synchronous pulse from the first pulse generator to the first signal line and transfer of a second column operation synchronous pulse from the second pulse generator to the second signal line, respectively.
In the semiconductor memory of the present invention, which has the above configurations, the timing of a synchronous pulse can be adjusted in conformity to a limiting factor to secure sufficiently an operational margin of a column system circuit, since a column operation synchronous pulses, which are different between read and write, is used. Hence, if the CAS latency is 3, tWR is smaller than in the case where the CAS latency is 2. Consequently, so that a problem such that a word line is reset before the data is completely written into a memory cell immediately before precharging is avoided.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.